Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the
third-generation Cadence® JasperGold® Formal
Verification Platform, featuring machine learning technology and core
formal technology enhancements. The updates to the platform address the
capacity and complexity challenges of today’s advanced SoC designs and
aim to improve verification throughput.
For more information on the new JasperGold Formal Verification Platform,
visit http://www.cadence.com/go/smartjasper.
Smart Proof Technology
The new JasperGold platform represents the latest stage of ongoing
proof-solver algorithm and orchestration improvements. This latest
platform incorporates Smart Proof Technology to improve verification
throughput for all JasperGold apps. Machine learning is used to select
and parameterize solvers to enable faster first-time proofs.
Additionally, machine learning is used to optimize successive runs for
regression testing, either on premises or in the cloud. With Smart Proof
Technology, proofs speed up by up to 4X, and up to 6X on regression runs.
“We measured averages of 2X faster proof performance out of the box and
5X faster regression runs across our design testcases with the new smart
JasperGold platform,” stated Mirella Negro Marcigaglia, Digital Design
Verification Manager at STMicroelectronics. “We are also seeing
non-converged properties reduced by over 50%. Combined, these
improvements significantly boost our verification productivity.”
Advanced Design Scalability
Given today’s larger and more complex SoC designs, the design
compilation process sets the maximum size of design, and the compute
resources necessary, to start formal analysis. The updated JasperGold
platform delivers more than 2X design compilation capacity with an
average of 50% reduction in memory usage during compilation, compared
with one year ago. Additionally, engineers can effectively scale design
capacity through advanced parallel compilation technologies that
optimally use available compute resources, and by running proofs on the
Cloud.
Formal Signoff Enhancements
The platform’s new formal coverage technologies let engineers perform IP
signoff purely within the JasperGold platform. These new formal signoff
technologies include improved proof-core accuracy, new techniques to
derive meaningful coverage from deep bug hunting and new formal coverage
analysis views. Together those features deliver signoff-quality formal
coverage metrics and enable multi-engine chip-level verification closure.
“The first-generation JasperGold platform pioneered commercial formal
verification and apps in the market, and the second generation
integrated Cadence technologies to establish formal verification with
mainstream users,” stated Ziyad Hanna, corporate vice president, Fabric
and Formal Solutions, System & Verification Group at Cadence. “Our
third-generation smart JasperGold platform significantly advances core
formal technology, applying machine learning to achieve tangible
performance and scalability benefits for our customers.”
The JasperGold Formal Verification Platform, part of the Cadence
Verification Suite, offers comprehensive coverage in the vManager™
Metric-Driven Signoff Platform, which combines JasperGold formal results
with Xcelium™ simulation and Palladium® emulation
metrics to speed overall verification closure. It supports the company’s
System Design Enablement strategy, which enables systems and
semiconductor companies to create complete, differentiated end products
more efficiently. The Cadence Verification Suite is comprised of the
best-in-class JasperGold, Xcelium, Palladium and Protium™
core engines, verification fabric technologies and solutions that
increase design quality and throughput, fulfilling verification
requirements for a wide variety of applications and vertical segments.
About Cadence
Cadence enables electronic systems and semiconductor companies to create
the innovative end products that are transforming the way people live,
work and play. Cadence software, hardware and semiconductor IP are used
by customers to deliver products to market faster. The company’s System
Design Enablement strategy helps customers develop differentiated
products—from chips to boards to systems—in mobile, consumer, cloud
datacenter, automotive, aerospace, IoT, industrial and other market
segments. Cadence is listed as one of Fortune Magazine’s 100 Best
Companies to Work For. Learn more at cadence.com.
© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.
Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks
are trademarks or registered trademarks of Cadence Design Systems, Inc.
All other trademarks are the property of their respective owners.
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