DESIGN AUTOMATION CONFERENCE — Ausdia, the leading developer of design
constraints verification and management solutions that complement timing
signoff for complex system-on-chip (SoC) designs, introduced an
exciting new capability to its comprehensive Timevision™ solution at the
56th Design Automation Conference (DAC) 2019.
Timevision FlatChecker closes the coverage gap between “flat” timing
closure and signoff and “timing-model/extracted timing models (ETM)”
based timing, enabling full-chip static timing analysis (STA) and
place-and-route engineers to ensure their ETM-based timing flows
correspond exactly to the complete, flat timing signoff.
Today, full-chip place-and-route specialists may wrestle with too many
over- or under-constrained paths at the full-chip SoC level, which can
affect PPA optimizations and prompt additional ECO iterations once flat
timing is enabled. Timevision FlatChecker pinpoints these variances
automatically without any designer input, and corrects issues with rich
rule-checking system and debugging features. Additionally, the
FlatChecker addition to Timevision can automatically generate new SDC
design constraints to enable ETM-based timing flows, if no ETM-enabled
SDC constraints are available.
SoC designs at 10nm and 7nm are getting larger and more complicated as
more and more functionality is placed into designs, requiring virtually
all designs to be implemented hierarchically. However, at the full-chip
level, designers must either use flat (full netlist) STA analysis, which
can extend turn-around-time (TAT), or use ETMs to reduce data volume and
provide significant TAT improvement. In order to enable full-chip
place-and-route timing closure, ETM-based methods become imperative,
requiring a solution to both generate and verify the SDC timing
constraints used so that PPA is optimal and final ECO spins are
minimized. FlatChecker ensures the SDC constraints used in ETM-based
place-and-route, and signoff, are equivalent to the fully-flat version
of the same design, as well as generating SDC constraints with selected
blocks changed to ETM format.
“Our customers are completing their SoC designs using hierarchical
design flows, and using every trick in the book to improve their
turn-around times (TAT) to complete place-and-route timing closure on
their chips,” said Ausdia president and CEO Sam Appleton. “We’re
introducing FlatChecker to enable the acceleration and verification of
ETM-based timing flows, as well as automatically generate SDC timing
constraints for ETM flows from the standard flat STA signoff.”
Timevision
is a comprehensive timing constraints development, verification and
management solution that complements all implementation and timing
signoff flows. It has the capacity to handle over 1 billion cells and
thousands of clocks. Timevision integrates with all aspects of the
design flow and is used before synthesis, before DFT insertion, before
place and route, and when signoff timing is being run. Timevision helps
designers create good SDC/TCL constraints and is a verification platform
for existing timing constraints.
Ausdia is highlighting Timevision and all add-on solutions in booth #
333 at the Design Automation Conference (DAC)
at the Las Vegas Convention Center, Las Vegas, NV from June 3 – 6, 2019.
About Ausdia
Ausdia
delivers standout timing constraint development, verification, and
management solutions that complement all implementation and timing
signoff flows. The company’s groundbreaking methodology and products
give system-on-chip (SoC) and integrated circuit (IC) developers a new
way to work, enabling massive productivity gains throughout the design
flow. Founded in 2006, the privately-held company is headquartered in
Sunnyvale, California.
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